Transcoder products have typically been limited to one or two channels. However, system-on-a-chip (SOC) technologies allow a transcoder product to integrate a larger number of transcoder channels into a single chassis via multiple transcoder SOC instances. The transcoder SOC instances may perform transcoding in parallel. A host computer processor unit (CPU) communicates with each of the transcoder SOC instances to coordinate the transcoding. Typically, each transcoder SOC instance requires that video streams be sent and received via a transport interface, such as a motion pictures experts group (MPEG) transport interface. This sends the video in an MPEG transport stream to the transcoder SOC instances using the MPEG standard. Although the MPEG standard is being used, each transcoder SOC instance may include a proprietary MPEG interface. The conversion is performed via field programmable gate array (FPGA) logic to convert video into the MPEG transport stream. The use of proprietary interfaces also complicates the logic as the MPEG transport stream must comply with the proprietary interface. Also, the host CPU sends control commands via a peripheral controller interface (PCI) bus to the transcoder SOC instances. Sending control commands using the PCI bus requires PCI bridge silicon. The use of FPGAs and the PCI bus increases the cost of the transcoder product. Also, the host CPU coordinates the sending of the MPEG transport stream to the transcoder SOC instances and also the control commands via the PCI bus. This causes a bottleneck especially when the host CPU is coordinating the transcoding of video between a large number of transcoder SOC instances.